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1 ? ISL6225 dual mobile-friendly pwm controller with ddr memory option the ISL6225 dual pwm controller delivers high efficiency and tight regulation from two voltage regulating synchronous buck dc/dc converters. the ISL6225 pwm power supply controller was designed especially for ddr dram, sdram, and graphic chipset applications in high performance desknote pcs, notebook pcs, sub-notebook pcs, and pdas. automatic mode selection of constant-frequency synchronous rectification at heavy load, an d hysteretic diode-emulation at light load, assure high efficiency over a wide range of conditions. the hysteretic mo de of operation can be disabled separately on each pwm converter if constant-frequency continuous-conduction operation is desired for all load levels. efficiency is further enhanced by using the lower mosfet r ds(on) as the current sense element. voltage-feed-forward ramp m odulation, average current mode control, and internal feedbac k compensation provide fast response to input voltage and output load transients. input current ripple is minimized by channel to channel pwm phase shift of 0, 90, or 180 determined by input voltage and status of the ddr pin. the ISL6225 can control two independent output voltages adjustable from 0.9v to 5.5v or, by activating the ddr pin, transform into a complete ddr memory power supply solution. in ddr mode, ch2 output voltage vtt tracks ch1 output voltage vddq. ch2 output can both source and sink current, an essential power supply feature for ddr memory systems. the reference voltage vref required by ddr memory is generated as well. in dual power supply applications the ISL6225 monitors the output voltage of both ch1 and ch2. an independent pgood (power good) signal is asserted for each channel after the soft-start sequence ha s completed, and the output voltage is within 10% of the set point. in ddr mode ch1 generates the only pgood signal. built-in overvoltage protection prevents the output from going above 115% of the set point by holding the lower mosfet on and the upper mosfet off. when the output voltage decays below the overvoltage threshold, normal operation automatically resume s. once the soft-start sequence has completed, unde r-voltage protection may latch the ISL6225 off if either output drops below 75% of its set point value. adjustable overcurrent protection (ocp) monitors the voltage drop across the r ds(on) of the lower mosfet. if more precise current-sensing is required, an external current sense resistor may be used. features ? provides regulated output voltage in the range of 0.9v-5.5v - high efficiency over wide load range - synchronous buck converter with hysteretic operation at light load - inhibit hysteretic mode on one, or both channels ? complete ddr memory power solution - vtt tracks vddq/2 - vddq/2 buffered reference output ? no current-sense resistor required - uses mosfet r ds(on) - optional current-sense resistor for precision overcurrent ? under-voltage lock-out on v cc pin ? dual input voltage mode operation - operates directly from battery 5v to 24v input - operates from 3.3v or 5v system rail - vcc from 5v only ? excellent dynamic response - combined voltage feed-forward and average current mode control ? power-good signal for each channel ? 300khz switching frequency - 180 channel to channel phase operation for reduced input ripple when not in ddr mode - 0 channel to channel phase operation in ddr mode for reduced channel interference - 90 channel to channel phase operation for reduced input ripple in ddr mode when vin is at gnd. ? pb-free available applications ? mobile pcs ?pdas ? hand-held portable instruments ordering information part number temp. (c) package pkg. dwg. # ISL6225ca -10 to 85 28 ld ssop m28.15 ISL6225caz (note 1) -10 to 85 28 ld ssop (pb-free) m28.15 ISL6225caza (note 1) -10 to 85 28 ld ssop (pb-free) m28.15 notes: 1. intersil pb-free products employ special pb-free material sets; molding compounds/die attach materials and 100% matte tin plate termination finish, which is compatible with both snpb and pb-free soldering operations. intersil pb-free products are msl classified at pb-free peak reflow temperatures that meet or exceed the pb-free requirements of ipc/jedec j std-020b. 2. add ?-t? for tape and reel. data sheet june 2004 fn9049.6 caution: these devices are sensitive to electrosta tic discharge; follow proper ic handling procedures. 1-888-intersil or 321-724-7143 | intersil (and design) is a registered trademark of intersil americas inc. copyright ? intersil americas inc. 2002-2004. all rights reserved all other trademarks mentioned are the property of their respective owners. n o t r e c o m m e n d e d f o r n e w d e s i g n s r e c o m m e n d e d r e p l a c e m e n t : i s l 6 2 2 7 o r i s l 6 5 3 9
2 pinout ISL6225 ssop-28 top view gnd lgate1 pgnd1 phase1 ugate1 boot1 isen1 en1 vout1 vsen1 ocset1 soft1 ddr vin vcc pgnd2 phase2 ugate2 boot2 en2 vsen2 ocset2 soft2 pg2/ref pg1 lgate2 isen2 vout2 28 27 26 25 24 23 22 21 20 19 18 17 16 15 1 2 3 4 5 6 7 8 9 10 11 12 13 14 ISL6225
3 absolute maximum rati ngs thermal information bias voltage, v cc . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .+ 6.5v input voltage, v in . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +27.0v phase, ugate voltage . . . . . . . . . . . . . . gnd-5v (note 3) to 33v boot, isen voltage . . . . . . . . . . . . . . . . . . . . gnd-0.3v to +33.0v boot with respect to phase . . . . . . . . . . . . . . . . . . . . . . . . .+ 6.5v all other pins . . . . . . . . . . . . . . . . . . . . . . gnd -0.3v to v cc + 0.3v esd classification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . class 2 recommended operating conditions bias voltage, v cc . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +5.0v 5% input voltage, v in . . . . . . . . . . . . . . . . . . . . . . . . . . . +5.0v to +24.0v ambient temperature range . . . . . . . . . . . . . . . . . . . .-10c to 85c junction temperature range. . . . . . . . . . . . . . . . . . .-10c to 125c thermal resistance (typical, note 4) ja (c/w) ssop package . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78 maximum junction temperature (plastic package) . . . . . . . . 150c maximum storage temperature range . . . . . . . . . . . -65c to 150c maximum lead temperature (soldering 10s) . . . . . . . . . . . . . 300c (ssop - lead tips only) caution: stresses above those listed in ?absolute maximum ratings? may cause permanent damage to the device. this is a stress o nly rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. notes: 3. 200ns transient. 4. ja is measured with the component mounted on a high effective ther mal conductivity test board in free air. see tech brief tb379 f or details. electrical specifications recommended operating conditions, unless otherwise noted. parameter symbol test conditions min typ max units v cc supply bias current i cc lgatex, ugatex open, vsenx forced above regulation point, ddr = 0, vin > 5v -2.23.2ma shut-down current i ccsn --30 a v cc uvlo rising v cc threshold v ccu 4.3 4.65 4.75 v falling v cc threshold v ccd 4.1 4.35 4.45 v v in input voltage pin current (sink) i vin 10 - 30 a input voltage pin current (source) i vino --15-30 a shut-down current i vins --1 a oscillator pwm1 oscillator frequency f c 255 300 345 khz ramp amplitude, pk-pk v r1 v in = 16v, by design - 2 - v ramp amplitude, pk-pk v r2 v in = 5v, by design - 1.25 - v ramp offset v roff by design - 0.5 - v ramp/v in gain g rb1 v in 3v, by design - 125 - mv/v ramp/v in gain g rb2 1 v in 3v, by design - 250 - mv/v reference and soft-start internal reference voltage v ref -0.9- v reference voltage accuracy -1.0 - +1.0 % soft-start current during start-up i soft --5- a soft-start complete threshold v st by design - 1.5 - v ISL6225
4 pwm converters load regulation 0.0ma < i vout1 < 5.0a; 5.0v < v batt < 24.0v -2.0 - +2.0 % vsen pin bias current i vsen by design 50 80 120 na v out pin input impedance i vout v out = 5v 40 55 65 k ? undervoltage shut-down level v uvl fraction of the set point; ~2 s noise filter 70 - 85 % overvoltage shut-down v ovp1 fraction of the set point; ~2 s noise filter 110 - 130 % gate drivers upper drive pull-up resistance r 2ugpup v cc = 4.5v - 8 15 ? upper drive pull-down resistance r 2ugpdn v cc = 4.5v - 3.2 5 ? lower drive pull-up resistance r 2lgpup v cc = 4.5v - 8 15 ? lower drive pull-down resistance r 2lgpdn v cc = 4.5v - 1.8 3 ? power good and control functions power good lower threshold v pg- fraction of the set point; ~3 s noise filter -13 - -7 % power good higher threshold v pg+ fraction of the set point; ~3 s noise filter. guaranteed by design. 12 - 16 % pgoodx leakage current i pglkg v pullup = 5.5v - - 1 a pgoodx voltage low v pgood i pgood = -4ma - 0.5 0.85 v en - low (off) --0.8v en - high (on) 2.5 - - v ccm enforced (hysteretic operation inhibited) voutx pulled low - - 0.1 v automatic ccm/hysteretic operation enabled voutx connected to the output 0.9 - - v ddr - low (off) --0.8v ddr - high (on) 2.5 - - v ddr ref output voltage v ddref ddr = 1, i ref = 0...10ma 0.99* v oc2 v oc2 1.01* v oc2 v ddr ref output current i ddref ddr = 1. guaranteed by design. - 10 16 ma electrical specifications recommended operating conditions, unless otherwise noted. (continued) parameter symbol test conditions min typ max units ISL6225
5 functional pin description gnd (pin 1) signal ground for the ic. lgate1, lgate2 (pin 2, 27) these are outputs of t he lower mosfet drivers. pgnd1, pgnd2 (pin 3, 26) these pins provide the return connection for lower gate drivers. these pins are connec ted to sources of the lower mosfets of their respective converters. phase1, phase2 (pin 4, 25) the phase1 and phase2 points are the junction points of the upper mosfet sources, output filter inductors, and lower mosfet drains. connect these pins to the respective converter?s upper mosfet source. ugate1, ugate2 (pin 5, 24) these pins provide the gate drive for the upper mosfets. boot1, boot2 (pin 6, 23) these pins power the upper mosfet drivers of the pwm converter. connect this pin to the junction of the bootstrap capacitor with the cathode of the bootstrap diode. anode of the bootstrap diode is connected to the vcc pin. isen1, isen2 (pin 7, 22) these pins are used to monitor the voltage drop across the lower mosfet for current feedback and overcurrent protection. for precise current detection these inputs can be connected to the optional current sense resistors placed in series with the source of the lower mosfets. en1, en2 (pin 8, 21) these pins enable operation of the respective converter when high. when both pins are low, the chip is disabled and only low leakage current <1 a is taken from v cc and v in . these pins are to be connected together and switched at the same time. vout1, vout2 (pin 9, 20) these pins when connected to the converters? respective outputs provide the output voltage inside the chip to reduce output voltage excursion during hys/pwm transition. when connected to ground, these pins command forced converters operate in conti nuous conduction mode at all load levels. vsen1, vsen2 (pin 10, 19) these pins are connected to the resistive dividers that set the desired output voltage. the pgood, uvp, and ovp circuits use this signal to report output voltage status. ocset1 (pin 11) a resistor from this pin to ground sets the overcurrent threshold for the first controller. soft1, soft2 (pin 12, 17) these pins provide soft-start function for their respective controllers. when the chip is enabled, the regulated 5 a pull-up current source charges the capacitor connected from the pin to ground. the output vo ltage of the converter follows the ramping voltage on the soft pin. ddr (pin 13) this pin, when high, transforms dual channel chip into complete ddr memory solution. the ocset2 pin becomes an input to provide the r equired tracking function. the channel synchronization is changed from out-of-phase to in- phase. the pg2/ref pin become s the output of the vddq/ 2 buffered voltage that is used as a reference voltage by the second channel. vin (pin 14) provides battery voltage to the oscillator for feed-forward rejection of the input voltage variation. when connected to ground via 100k ? resistor while the ddr pin is high, this pin co mmands the out-of-phase 90 o channels synchronization for reduced inter-channel interference. pg1 (pin 15) pgood1 is an open drain output used to indicate the status of the output voltage. this pin is pulled low when the first channel output is not within 10% of the set value. pg2/ref (pin 16) this pin has a double function depending on the mode the chip is operating. when the chip is used as a dual channel pwm controller (ddr = 0), the pin provides a pgood2 function for the second channel. the pin is pulled low when the second channel output is not within 10% of the set value. in ddr mode (ddr = 1), this pin serves as an output of the buffer amplifier that provides vddq/2 reference voltage applied to the ocset2 pin. ocset2 (pin 18) in a dual channel application (ddr = 0), a resistor from this pin to ground sets the overcurrent threshold for the second controller. in the ddr application (ddr = 1), this pin sets the output voltage of the buffer amplifier and the second controller and should be connected to the center point of a divider from the vddq output. vcc (pin 28) this pin powers the controller. ISL6225
6 generic application circuits +v in v out1 v out2 +1.80v +1.20v +3.3v to +24v l1 q1 q2 ocset1 ddr figure 1. ISL6225 application circuit for two channel power supply pwm1 pwm2 l2 q3 q4 c2 ocset2 vcc en2 en1 +5v enable + c1 + figure 2. ISL6225 application circuit for complete ddr memory power supply +v in vddq vtt +2.50v +1.25v +3.3v to +24v l1 q1 q2 ocset1 ddr pwm1 pwm2 l2 q3 q4 ocset2 vcc enable en2 en1 +5v vref +1.25v pg2/vref c1 + c2 + ISL6225
7 block diagram error amp 1 ? v hys =15mv vsen1 hysteretic comparator 1 mode change comp 1 300k ? pwm1 + 0.9v reference isen1 100 ? sample current sample current phase1 pgnd1 ugate1 boot1 lgate1 vcc + 0.9v reference ocset1 1/3 ocset1 1/32 isen1 error amp 2 adaptive dead-time ? v hys =15mv vsen2 hysteretic comparator 2 mode change comp 2 1m ? 15.2pf 1.3pf 500k ? 300k ? pwm2 + 0.9v reference isen2 100 ? sample current sample current phase2 pgnd2 ugate2 boot2 lgate2 vcc diode emulation v/i sample timing + 0.9v reference ocset2 1/3 ocset2 1/32 isen2 ddr vin vcc duty cycle ramp generator pwm channel phase control oc2 oc1 ddr=0 ddr=1 ddr vtt ddr=0 ddr=1 8 clock cycles same state for required to latch over-current fault 8 clock cycles same state for required to change pwm or hys mode 8 clock cycles same state for required to change pwm or hys mode 8 clock cycles same state for required to latch over-current fault vcc pg1 reference ov uv pgood ddr vref buffer amp ddr=1 ddr=0 1.3pf 500k ? 1m ? 15.2pf ov uv pgood vout1 vout2 pwm/hys transition adaptive dead-time diode emulation v/i sample timing pwm/hys transition volts/sec clamp volts/sec clamp oc1 ddr por fault latch bias supplies reference enable soft-start gnd en1 en2 ref/pg2 soft1 soft2 ddr mode control oc2 ddr en1 en2 vin ch1 ch2 011 0 ? 24.0v 180o 111 90o 4.2 < vin < 24.0v vin to gnd 0o + + - - - + - + - + - + - + + - + - + - - + + - - + + -
8 description operation the ISL6225 is a dual channel pwm controller intended for use in power supplies for graphic chipset, sdram, ddr dram or other low voltage power applications in modern notebook and sub-notebook pcs. the ic integrates two control circuits for two synchronous buck converters. the output voltage of each controller can be set in the range of 0.9v to 5.5v by an external re sistive divider. out-of-phase operation with 180 degree phase shift reduces input current ripple. the synchronous buck converters can operate from either an unregulated dc source such as a notebook battery with a voltage ranging from 5.0v to 24v, or from a regulated system rail of 3.3v or 5v. in either mode of operation the controller is biased from the +5v source. the controllers operate in the current mode with input voltage feed-forward for simplified feedback loop compensation and reduced effe ct of the input voltage variation. an integrated feedback loop compensation dramatically reduces the num ber of external components. depending on the load level, c onverters can operate either in a fixed-frequency mode or in a hysteretic mode. switch- over to the hysteretic mode op eration at light loads improves the converters' efficiency and prolongs battery run time. the hysteretic mode of operatio n can be inhibited independently for each channel if a variable frequency operation is not desired. the ISL6225 has a special means to rearrange its internal architecture into a complete ddr solution. when ddr input is set high, the second channel can provide the capability to track the output voltage of t he first channel. the buffered reference voltage required by ddr memory chips is also provided. initialization the power-on reset (por) func tion continually monitors the bias supply voltage on the v cc pin and initiates soft-start operation after the input supply voltage exceeds 4.5v. should this voltage drop lower than 4.0v, the por disables the chip. soft-start when soft-start is initiated, the voltage on the soft pin starts to ramp gradually due to the 5 a current sourced into the external soft-start capacitor. the output voltage starts to follow the soft-start voltage. when the soft pin voltage reaches a level of 0.9v, the output voltage comes into regulation while the soft-start pin voltage continues to rise. when the soft voltage reaches 1.5v, the power good (pgood), the mode control, and the fault functions are enabled, as depicted in figure 3. this completes the soft-start sequence. further rise of pin voltage does not affect the output voltage. during the soft- start, the converter always operates in continuous conduction mode independently of the load level or fccm pin potential. the soft-start time (the time from the moment when en becomes high to the moment when pgood is reported) is determined by the following equation. the time it takes the output voltage to come into regulation can be obtained from the following equation. having such a spread between the time when the output voltage reaches the regulation point and the moment when pgood is reported allows fo r a fault-safe test mode by means of an external circuit that clamps the soft pin voltage on the level 0.9v < v soft < 1.5v. output voltage program the output voltage of either channel is set by a resistive divider from the output to ground. the center point of the divider is connected to vsen pin as show n in figure 4. the output voltage value is determined by the following equation. where 0.9v is the va lue of the internal reference. the vsen pin voltage is also used by the controller for the power good function and to detect undervoltage and overvoltage conditions. figure 3. start up ch3 1.0v ch2 2.0v ch4 5.0v m1.00ms ch1 5.0v 3 2 4 1 en 0.9v 1.5v soft vout pgood t soft 1.5v csoft 5 a ---------------------------------- = t rise 0.6 t soft = v o 0.9v r1 r2 + () ? r2 --------------------------------------------- - =
9 automatic operation mode control in nominal currents the synchronous buck converter operates in continuous-conduction constant-frequency mode. this mode of operation achieves higher efficiency due to the substantially lower voltage drop across the synchronous mosfet compared to a schottky diode. in contrast, continuous-conduction operation with load currents lower than the inductor critical value results in lower efficiency. in this case, during a fraction of a switching cycle, the direction of the inductor current changes to the opposite, actively discharging the output filter capacitor. to maintain the output voltage in regulation, the discharged energy should be restored dur ing the consequent cycle of operation by the cost of increased circulating current and losses associated with it. the critical value of the induct or current can be estimated by the following expression: to improve converter efficiency at loads lower than critical, the switch-over to variable fr equency hysteretic operation with diode emulation is implemented into the pwm scheme. the switch-over is provided automatically by the mode control circuit that constantly monitors the inductor current and alters the way the pwm signal is generated. the voltage across the synchronous mosfet at the moment of time just before the upper-mosfet turns on is monitored for purposes of mode change. when the converter operates at currents higher than critical, this voltage is always negative. in currents lower than critical, the voltage is always positive. th e mode control circuit uses a sign of voltage across the synchronous devices to determine if the load current is higher or lower than the critical value. to prevent chatter between operating modes, the circuit looks for eight contiguous signals of the same polarity before it makes the decision to perform a mode change. the same algorithm is true for both cc m-hysteretic and hysteretic- ccm transitions. hysteretic operation when the critical inductor curre nt is detected, the converter enters hysteretic mode. the pwm comparator and the error amplifier that provided control in the ccm mode are inhibited and the hysteretic comparator is now activated. a change is also made to the gate logi c. in hysteretic mode the synchronous rectifier mosfet is controlled in diode emulation mode, hence conduction in the second quadrant is prohibited. figure 4. output voltage program r2 r1 ugate lgate ISL6225 l1 q1 q2 c1 vout vsen vin r cs isen ocset r oc cz i hys v in v o ? () v o ? 2f sw l o v in ? ? ? ----------------------------------------------------- = figure 5. ccm - hysteretic transition pwm hysteretic 1 2 3 4 5 6 7 8 vout iind phase operation mode of t t t t comp figure 6. hysteretic - ccm transition pwm hysteretic 1 2 3 4 5 6 7 8 vout iind phase comp operation mode of t t t t ISL6225
10 the hysteretic comparator init iates the pwm signal when the output voltage gets below the lower threshold and terminates the pwm signal when the output voltage rises above the upper threshold. a spread or hysteresis between these two thresholds determines the switching frequency and the peak value of the inductor current. the transition to constant frequency ccm mode happens when the inductor current increases above the critical value: where, ? v hys = 15mv, is a hysteretic comparator window, esr is the equivalent series resistance of the output capacitor. because of differ ent control mechanisms, the value of the load current where transition into ccm operation takes place is usually higher compared to the load level at which transition into hysteretic mode had occurred. v out pin and forced continuous conduction mode (fccm) the controller has the flexibilit y to operate a converter in fixed-frequency constant conduction mode (ccm), or in hysteretic mode. connecting the v out pin to gnd will inhibit hysteretic mode; this is call ed forced constant conduction mode (fccm). connecting the v out pin to the converter output will allow transition between ccm mode and hysteretic mode. when the v out pin is connected to the converter output, a circuit is activated that smooth s the transition from hysteretic mode to ccm mode. while in hysteretic mode, this circuit prepositions the pwm error amplifier output to a level close to that needed to provide the approp riate pwm duty cycle required for regulation. this is a much more desirable state for the pwm error amplifier at mode transition, as opposed to being in saturation which requires a period of time to slew to the required level. such dual function of the v out pin enhances applicability of the controller and allows for lower pin count. feedback loop compensation to reduce the number of external components and remove the burden of determining compensation components from a system designer, both pwm controllers have internally compensated error amplifiers. to make internal compensation possible several design measures where taken. first, the ramp signal applied to the pwm comparator is proportional to the input volt age provided via the vin pin. this keeps the modulator gain constant when the input voltage varies. second, the load current proportional signal is derived from the voltage drop across the lower mosfet during the pwm time interval and is added to the amplified error signal on the comparator input. this effectively creates an internal current control lo op. the resistor connected to the isen pin sets the gain in the current feedback loop. the following expression estimates the required value of the current sense resistor depending on the maximum load current and the value of the mosfet?s r ds(on) . due to implemented current feedback, the modulator has a single pole response with -1 slope at a frequency determined by the load, where: ro is load resistance and co is load capacitance. for this type of modulator, a type 2 compensation circuit is usually sufficient. figure 7 shows a type 2 amplifier and its response along with the responses of the cu rrent mode modulator and the converter. the type 2 amplifier, in addition to the pole at origin, has a zero-pole pair that causes a flat gain region at frequencies between the zero and the pole: ; this region is also associ ated with phase ?bump? or reduced phase shift. the amount of phase shift reduction depends on how wide the region of flat gain is and has a maximum value of 90 o . to further simplify the converter compensation, the modulator gain is kept independent of the input voltage variation by providing feed-forward of v in to the oscillator ramp. i ccm ? v hys 2esr ? --------------------- - r cs i max r ds on () ? 75 a --------------------------------------------- - 100 ? ? = f po 1 2 r o c o ?? ---------------------------------- = f z 1 2 r 2 c 1 ?? ------------------------------- 6khz == f p 1 2 r 1 c 2 ?? ------------------------------- 600khz == figure 7. feedback loop compensation r1 r2 c1 c2 f po f z f p f c modulator ea type 2 ea g ea = 14db g m = 18db converter ISL6225
11 the zero frequency, the amplifier high-frequency gain, and the modulator gain are chosen to satisfy most typical applications. the crossover frequency will appear at the point where the modulator att enuation equals the amplifier high frequency gain . the only task that the system designer has to complete is to specify the output filter capacitors to position the load main pole somewhere within one decade lower than the amplifier zero fr equency. with this type of compensation plenty of phase ma rgin is easily achieved due to zero-pole pair phase ?boost?. conditional stability may occur only when the main load pole is positioned too much to the left side on the frequency axis due to excessive output filter capacitance. in this case, the esr zero placed within 10khz...50khz range gives some additional phase ?boost?. some phase boost can also be achieved by connecting capacitor c z in parallel with the upper resistor r1 of the divider that sets the output voltage value, as shown in figure 4. gate control logic the gate control logic translates generated pwm signals into gate drive signals providing necessary amplification, level shift, and shoot-trough protection. also, it bears some functions that help to optimiz e the ic performance over a wide range of the operational conditions. as mosfet switching time can very dramatically from type to type and with the input voltage, the ga te control logic provides adaptive dead time by monitoring real gate waveforms of both the upper and the lower mosfets. dual-step conversion the ISL6225 dual channel controller can be used either in power systems with a single-s tage power conversion when the battery power is conver ted into the desired output voltage in one step, or in the systems where some intermediate voltages are initiall y established. the choice of the approach may be dictated by the overall system design criteria or simply to be a matter of voltages available to the system designer, like in the case of pci card applications. when the power input voltage is a regulated 5v or 3.3v system bus, the feed-forward ramp may become too shallow, which creates the possi bility of duty-factor jitter especially in a noisy environment. the noise susceptibility when operating from low level regulated power sources can be improved by connecting the vin pin to ground. the feed- forward ramp generator will be internally reconnected from the vin pin to the v cc pin and the ramp slew rate will be doubled. application circuits for dual-step power conversion are presented in figures 11 through 15. protections the converter output is moni tored and protected against extreme overload, short ci rcuit, overvoltage, and undervoltage conditions. a sustained overload on the output sets the pgood low and latches-off the whole chip. the controller operation can be restored by cycling the vcc voltage or an enable (en) pin. overcurrent protection both pwm controllers use the lower mosfet?s on-resistance {r ds(on) } to monitor the current for protection against shorted outputs. the sensed current from the isen pin is compared with a current set by a resistor connected from the ocset pin to ground. where, i oc is a desired overcurrent protection threshold and r cs is the value of the current sense resistor connected to the i sen pin. if the lower mosfet current exceeds the overcurrent threshold, a pulse skipping circ uit is activated. the upper mosfet will not be turned on as long as the sensed current is higher then the thre shold value. this limits the current supplied by the dc voltage source. this condition keeps on for eight clock cycles after the overcurrent comparator was tripped for the first time. if after these first eight clock cycles the current exceeds the overcurrent threshold again in a time interval of another eight clock cycles, the overcurrent protec tion latches and disables the chip. if the overcurrent condition goes away during the first eight clock cycles, normal o peration is restored and the overcurrent circuit resets itself sixteen clock cycles after the overcurrent threshold was exc eeded the first time, figure 8. r ocset 9.6v r cs 100 ? + () ? i oc r ? ds on () --------------------------------------------------------- - = figure 8. overcurrent protection waveforms 3 1 2 shutdown il vout ch3 1.0a ? pgood m 10.0s ch2 100mv ch1 5.0v 8 clk ISL6225
12 if load step is strong enough to pull output voltage lower than the undervoltage threshold, the chip shuts down immediately. because of the nature of the used current sensing technique, and to accommodate wide range of the r ds(on) variation, the value of the overcurrent threshold should represent overload current about 150%...180% of the nominal value. if more precis e current protection is desired, a current sense resistor plac ed in series with the lower mosfet source may be used. overvoltage protection should the output voltage increa se over 115% of the normal value due to the upper mosfet failure, or other reasons, the overvoltage protection comparator will force the synchronous rectifier gate driver high. this action actively pulls down the output voltage and eventually attempts to blow the battery fuse. as soon as the output voltage drops below the threshold, the ovp comparator is disengaged. this ovp scheme provides a ?soft? crowbar function which helps to tackle severe load transients and does not invert the output voltage when activated - a common problem for ovp schemes with a latch. over-temperature protection the chip incorporates an ove r-temperature protection circuit that shuts the chip down when the die temperature of 150c is reached. normal operation restores at die temperatures below 125c through t he full soft-start cycle. ddr application double data rate (ddr) memory chips are expected to take the place of traditional memory in many newly designed computers, including high-end notebooks, due to increased throughput. a novel feature associated with this type of memory is new referencing and data bus termination techniques. these techniques employ a reference voltage, vref, that tracks the cent er point of vddq and vss voltages and an additional vtt power source to which all terminating resistors are conn ected. despite the additional power source, the overall memory power consumption is reduced compared to traditional termination. the added power source has a cluster of requirements that should be observed and considered. due to reduced differential thresholds of ddr memory, the termination power supply voltage, vtt, shall closely track vddq/2 voltage. another very important feature for the termination power supply is a capability to equally operate in sourcing and sinking modes. the vtt supply shall regulate the output voltage with the same degree of precision when current is floating from the supply to the load and when the current is diverted back from the load into the power supply. the last mode of operation usually conflic ts with the way most pwm controllers operate. the ISL6225 dual channel pwm controller possesses several important means that allow reconfiguration for this particular application and prov ide all three voltages required in ddr memory-compliant computer. to reconfigure the ISL6225 for a complete ddr solution, the ddr pin shall be permanently set high. the simplest way to do that is to connect it to the v cc rail. this activates some functions inside the chip that are specific to the ddr memory power needs. in the ddr application presented in figures 14 and 15, the first controller regulates the vddq rail to 2.5v. the output voltage is set by an external divider r3 and r5. the second controller regulates the vtt rail to vddq/2. the ocset2 pin function is now different. the pin serves now as an input that brings vddq/2 voltage created by r4 and r6 divider inside the chip. that effectively provides a tracking function for the vtt voltage. the pg2 pin function is also different in ddr mode. this pin becomes the output of the buffer, which input is connected via the ocset2 pin to the cent er point of the r/r divider from the vddq output. the buffer output voltage serves as 1.25v reference for the ddr memory chips. current capability of this pin is about 10ma. for the vtt channel some control and protective functions can be significantly simplified as this output is derived from the vddq output. for exam ple, the overcurrent and overvoltage protections for the second controller are disabled when the ddr pin is set high. the hysteretic mode of operation is also disabled on the vtt channel to allow sinking capability to be independent from the load level. as the vtt channel tracks the vddq/2 voltage, the soft-start function is not required and the soft2 pin may be left open. channel synchroni zation in ddr applications presence of two pwm controllers on the same die require channel synchronization to reduce inter channel interference that may cause the duty factor jitter and increased output ripple. the pwm controller is mostly susceptible to noise when an error signal on the input of the pwm comparator approaches the decision making point. false triggering can occur causing jitter and affecting the output regulation. out-of-phase operation is a common approach to synchronize dual channel converters as it reduces an input current ripple and provides a minimum interference for channels that control different voltage levels. when used in ddr application with cascaded converters (vtt generated from vddq), the turn-on of the upper mosfet in the vddq channel happens to be just before the decision making point in the vtt channel that is running with a duty-factor close to 50%, as in figure 10. ISL6225
13 this makes out-of-phase channel synchronization undesirable when one of the channels is running on a duty- factor of 50%. inversely, the in-phase channel arrangement does not have this drawback. points of decision are far from noisy moments of time in both sourcing and sinking modes of operation for v in = 7.5v to 24v as it is shown in figure 9. in the case when power for vddq is taken from the +5v system rail, as figure 10 shows, both in-phase and out-of- phase approaches are susceptible to noise in the sourcing mode. noise immunity can be improved by operating the vtt converter with a 90 o phase shift. as the time diagrams in figure 10 show, the points of concern are always about a quarter of the period away from the noise emitting transitions. several ways of synch ronization are implemented into the chip. when the ddr pin is conne cted to gnd, the channels operate 180 o out-of-phase. in the ddr mode when the ddr pin is connected to v cc , the channels operate either in- phase when the v in pin is connected to the input voltage source, or with 90 o phase shift if the vin pin is connected to gnd. ISL6225 dc-dc con verter application circuits figures 11 and 12 show application circuits of a dual channel dc/dc converter for a notebook pc. the power supply in figure 11 provides +2.5v and +1.8v for memory and graphic interface chipset from +5.0v to +24v battery voltage. figure 12 shows the power supply that provides +2.5v and +1.8v for memory and graphic interface chipset from +5.0v system rail. figure 13 shows an application circuit for a single-output split input power supply with current sharing for advanced graphic card applications. figure 14 and 15 show application circuits of a complete power solution for ddr memory that becomes a preferred choice in modern computers. the power supply shown in figure 14 generates +2.5v vddq voltage from +5.0v to +24v battery voltage. the +1.25v vtt termination voltage tracks vddq/2 and is derived from +2.5v vddq. to complete the ddr memory powe r requirements, the +1.25v reference voltage is also provided. the pg2 pin serves as an output for the reference voltage in this mode. figure 15 depicts the ddr solution in the case where the 5v system rail is used as a primary voltage source. for detailed information on the circuit, including a bill-of- materials and circuit board description, see application note an9995. also see intersil?s w eb site (http://www.intersil.com) for the latest information. figure 9. channel interference v in = 7.5v...24v out-of-phase in-phase sourcing sinking sinking sourcing vtt vtt 300khz clock vddq figure 10. channel interference v in = 5v out-of-phase in-phase sourcing sinking sinking sourcing 300khz clock vtt vtt vddq 90 o phase shift sinking sourcing vtt ISL6225
14 ddr ISL6225 gnd 3 5 9 25 2 13 10 20 8 11 vin 22 cr1 4 19 17 6 3.0a vsen1 ugate1 phase1 1/2 fds6912a pgnd1 lgate1 isen1 bat54 boot1 2/2 fds6912a vout1 en1 ocset1 +5v 1 18 100k 12 pg1 7 27 24 23 14 l1 16 pg2/ref 21 soft1 26 q1 c8 + 10nf c3 10nf c4 r7 100k r8 330 f 17.8k r3 q2 2.00k r1 10k r5 c6 0.15 f vcc cr2 vsen2 ugate2 phase2 1/2 fds6912a pgnd2 lgate2 isen2 +5.0v to +24v boot2 2/2 fds6912a vout2 en2 ocset2 l2 soft2 q3 c9 + 330 f 10k r4 q4 2.00k r2 c7 0.15 f 28 15 enable power good ch1 power good ch2 wt1 bat54 wt1 vin vcc 100k r9 vpullup 10k r6 c2 + 10 f c1 1.0 f c5 + 10 f +2.50v 2.0a +1.80v c10 + 10 f 15nf c11 15nf c12 figure 11. dual output applicatio n circuit for one-step conversion 10 h 10 h ISL6225
15 ddr ISL6225 gnd 3 5 9 25 2 13 10 20 8 11 vin 22 cr1 4 19 17 6 vsen1 ugate1 phase1 1/2 fds6912a pgnd1 lgate1 isen1 bat54 boot1 2/2 fds6912a vout1 en1 ocset1 +5v 1 18 100k 12 pg1 7 27 24 23 14 l1 16 pg2/ref 21 soft1 26 q1 c8 + 10nf c3 10nf c4 r7 100k r8 330 f 17.8k r3 q2 2.00k r1 10k r5 c6 0.15 f vcc cr2 vsen2 ugate2 phase2 1/2 fds6912a pgnd2 lgate2 isen2 boot2 2/2 fds6912a vout2 en2 ocset2 l2 soft2 q3 c9 + 330 f 10k r4 q4 2.00k r2 c7 0.15 f 28 15 enable power good ch1 power good ch2 wt1 bat54 wt1 vcc 100k r9 vpullup 10k r6 c5 + 10 f 2.0a +1.80v 3.0a +2.50v c2 + 10 f c1 1.0 f 15nf c11 15nf c12 figure 12. dual output application circuit for two-step conversion 4.7 h 4.7 h ISL6225
16 ddr ISL6225 gnd 3 5 9 25 2 13 10 20 8 11 vin 22 cr1 4 19 17 6 8.0a vsen1 ugate1 phase1 1/2 fds6912a pgnd1 lgate1 isen1 bat54 boot1 2/2 fds6912a vout1 en1 ocset1 1 18 100k 12 pg1 7 27 24 23 14 l1 16 pg2/ref 21 soft1 26 q1 c8 + 10nf c3 10nf c4 r7 100k r8 330 f 6.65k r3 q2 2.00k r1 10k r5 c6 0.15 f vcc cr2 vsen2 ugate2 phase2 1/2 fds6912a pgnd2 lgate2 isen2 +12v boot2 2/2 fds6912a vout2 en2 ocset2 l2 soft2 q3 c9 + 330 f 6.65k r4 q4 2.00k r2 c7 0.15 f 28 15 enable power good ch1 power good ch2 wt1 bat54 wt1 vin 100k r9 vpullup 10k r6 c2 + 10 f c1 1.0 f c5 + 10 f +1.50v +5v vcc c10 + 330 f c11 + 330 f 0.01 r10 0.01 r11 15nf c12 15nf c13 figure 13. single-output split input power supply 4.7 h 10 h ISL6225
17 ddr ISL6225 gnd 3 5 9 25 2 13 10 20 8 11 vin 22 cr1 4 19 17 6 vsen1 ugate1 phase1 1/2 fds6912a pgnd1 lgate1 isen1 bat54 boot1 2/2 fds6912a vout1 en1 ocset1 +5v 1 18 100k 12 pg1 7 27 24 23 14 l1 16 pg2/ref 21 soft1 26 q1 c8 + 10nf c3 r7 330 f 17.8k r3 q2 2.49k r1 10k r5 c6 0.15 f vcc cr2 vsen2 ugate2 phase2 1/2 fds6912a pgnd2 lgate2 isen2 +5.0v to +24v boot2 2/2 fds6912a vout2 en2 ocset2 l2 soft2 q3 c9 + 330 f 10k r4 q4 1.00k r2 c7 0.15 f 28 15 enable power good ch1 vref wt1 bat54 wt1 vin vcc 100k r9 vpullup 10k r6 c2 + 10 f c1 c5 + 10 f +2.50v 3.0a +1.25v ~ 6.0a 3.0a vddq vtt c4 1.0 f 10nf c10 15nf c12 c11 + 10 f figure 14. application circuit for complete ddr memory power solution with one-step conversion 4.6 h 4.7 f 1.5 h ISL6225
18 ddr ISL6225 gnd 3 5 9 25 2 13 10 20 8 11 vin 22 cr1 4 19 17 6 vsen1 ugate1 phase1 1/2 fds6912a pgnd1 lgate1 isen1 bat54 boot1 2/2 fds6912a vout1 en1 ocset1 +5v 1 18 100k 12 pg1 7 27 24 23 14 l1 16 pg2/ref 21 soft1 26 q1 c8 + 10nf c3 r7 330 f 17.8k r3 q2 2.49k r1 10k r5 c6 0.15 f vcc cr2 vsen2 ugate2 phase2 1/2 fds6912a pgnd2 lgate2 isen2 boot2 2/2 fds6912a vout2 en2 ocset2 l2 soft2 q3 c9 + 330 f 10k r4 q4 1.00k r2 c7 0.15 f 28 15 enable power good ch1 vref wt1 bat54 wt1 vcc 100k r9 vpullup 10k r6 c1 c11 + 10 f +2.50v 3.0a +1.25v ~ 6.0a 3.0a vddq vtt c4 1.0 f 10nf c5 15nf c12 + c2 + 10 f c10 10 f figure 15. application circuit for complete ddr memory power solution with two-step conversion 1.5 h 4.7 f 4.6 h ISL6225
19 all intersil u.s. products are manufactured, asse mbled and tested utilizing iso9000 quality systems. intersil corporation?s quality certifications ca n be viewed at www.intersil.com/design/quality intersil products are sold by description only. intersil corpor ation reserves the right to make changes in circuit design, soft ware and/or specifications at any time without notice. accordingly, the reader is cautioned to verify that data sheets are current before placing orders. information furnishe d by intersil is believed to be accurate and reliable. however, no responsibility is assumed by intersil or its subsidiaries for its use; nor for any infringements of paten ts or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of intersil or its subsidiari es. for information regarding intersil corporation and its products, see www.intersil.com ISL6225 shrink small outline plastic packages (ssop) quarter size outline plastic packages (qsop) notes: 1. symbols are defined in the ?mo series symbol list? in section 2.2 of publication number 95. 2. dimensioning and tolerancing per ansi y14.5m - 1982. 3. dimension ?d? does not include mo ld flash, protrusions or gate burrs. mold flash, protrusion and gate burrs shall not exceed 0.15mm (0.006 inch) per side. 4. dimension ?e? does not include inte rlead flash or protrusions. inter- lead flash and protrusions shall not exceed 0.25mm (0.010 inch) per side. 5. the chamfer on the body is optional. if it is not present, a visual in- dex feature must be located within the crosshatched area. 6. ?l? is the length of terminal for soldering to a substrate. 7. ?n? is the number of terminal positions. 8. terminal numbers are shown for reference only. 9. dimension ?b? does not include dam bar protrusion. allowable dam- bar protrusion shall be 0.10mm (0.004 inch) total in excess of ?b? dimension at maximum material condition. 10. controlling dimension: inches. c onverted millimeter dimensions are not necessarily exact. index area e d n 123 -b- 0.17(0.007) c a m bs e -a- b m -c- a1 a seating plane 0.10(0.004) h x 45 c h 0.25(0.010) b m m l 0.25 0.010 gauge plane a2 m28.15 28 lead shrink small outline plastic package (0.150? wide body) symbol inches millimeters notes min max min max a 0.053 0.069 1.35 1.75 - a1 0.004 0.010 0.10 0.25 - a2 - 0.061 - 1.54 - b 0.008 0.012 0.20 0.30 9 c 0.007 0.010 0.18 0.25 - d 0.386 0.394 9.81 10.00 3 e 0.150 0.157 3.81 3.98 4 e 0.025 bsc 0.635 bsc - h 0.228 0.244 5.80 6.19 - h 0.0099 0.0196 0.26 0.49 5 l 0.016 0.050 0.41 1.27 6 n28 287 0 8 0 8 - rev. 1 6/04

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